1. Field of the Invention
The invention relates to a method for patterning an HfO2-containing dielectric, and more particularly, to a method for patterning an HfO2-containing gate dielectric without damaging STI positioned on the same wafer.
2. Description of the Prior Art
For realizing the low power MOS transistor at the 65 nm node and beyond, it is necessary to reduce the gate leakage current for thinner gate dielectrics. The introduction of high-k gate material would be advantageous for extending current MOS technology. After several years of work, many research groups are now focusing on hafnium (Hf) based material and are evaluating the natural of these materials extensively. Among the considerable Hf-based materials, HfO2 is often evaluated to be combined into a metal gate structure.
However, HfO2-containing dielectric (including HfO2, HfSiO, HfSiON, HfAlO, and so on) is known for more difficult to be pattern etched comparing to SiO2 based dielectric. The conventional method of etching the HfO2-containing dielectric involves using a strong acid, such as 49% HF solution. When using the 49% HF solution to etch the HfO2-containing dielectric, a SiO2 layer, such as a shallow trench isolation (STI) layer, will be also removed. Furthermore, the etching rate of the SiO2 layer is much higher than that of the HfO2-containing dielectric, and the SiO2 layer will be seriously damaged while patterning the HfO2-containing dielectric.
Another conventional method of etching the HfO2-containing dielectric is using a high insert gas plasma with more than 60% Ar. The insert gas plasma has no selectivity while etching, and may also result in the SiO2 layer being damaged during over-etch.
Please refer to FIGS. 1 and 2, which show a conventional etching process of the HfO2-containing dielectric. An STI layer 18 is formed on a wafer 10, and an HfO2-containing gate dielectric 12 covers the wafer 10 and the STI layer 18. A gate electrode 16 is formed on the HfO2-containing gate dielectric 12, and two spacers 14 are formed beside the gate electrode 16. As shown in FIG. 2, the conventional etching process such as using the strong acid or the insert gas plasma is performed to remove portions of the HfO2-containing gate dielectric 12. The etching selectively between the HfO2-containing gate dielectric 12 and the STI layer 18 is too low to bring serious damages atop the STI layer 18. As a result, the isolation effect of the STI layer 18 is reduced.